The present invention relates to a one-chip LSI (memory-logic LSI) including a general memory and a logic.
In recent years, a one-chip LSI has been developed, which includes a memory for storing data and a logic for processing data. As regards the one-chip LSI, the following matters should be taken into consideration: to maintain high-integration density of a general memory and high-accessibility of a logic in integrating them in one chip; to make a design as easy as in the case of an ASIC (Application Specific Integrated Circuit) for an LSI designer; and to save the manufacturing cost.
FIG. 1 is a schematic diagram showing a chip layout of a conventional memory-logic LSI.
A logic section 1, a data input/output section 2, and a memory macro section 3 are formed on the main surface of an LSI chip 10.
The memory macro section 3 is arranged in a central portion of the main surface of the LSI chip 10. The layout within the memory macro section 3 is basically the same as that in the conventional general memory which has been developed and produced.
The memory macro section 3 comprises a data input/output circuit 5 for transmitting data between the logic section 1 and the memory macro section 3. The data input/output circuit 5 is arranged along a part of the periphery of the memory macro section 3.
The logic section 1 surrounds the memory macro section 3. The logic section 1 comprises a gate array, a standard cell and a mega-cell. A test control circuit for use in a test of the memory macro section 3 is formed in the logic section 1.
The data input/output section 2, formed along the edges of the LSI chip 10, is used to transmit data between the interior of the LSI chip and an external device. The data input/output section 2 comprises data input/output circuits, data input/output pads and protecting circuits.
The memory-logic LSI as described above is advantageous in that the number of bits which is simultaneously input to and output from the memory macro section 3, i.e., the bit type (.times.n), can be set to, for example, 8 times or 16 times of the number of bits in the case of a general memory (DRAM), since data transmission between the memory and the logic circuit is performed inside the chip.
According to the aforementioned memory-logic LSI, it is possible to provide a memory macro section 3 of a super-multiple bit type, e.g., 256 bit type or 1 kilobit type. Accordingly, the rate of data transfer between the logic section 1 and the memory macro section 3 can be improved, which allows high-speed data processing.
For this reason, the memory-logic LSI is very much suitable for use in an image processing unit of a PC (Personal Computer) or EWS (Engineering Work Station).
In the memory-logic LSI shown in FIG. 1, the memory macro section 3 is designed by an LSI designer so as to have a memory capacity (e.g., 16 MB) and a bit type (e.g., .times.256) to satisfy the user's requirements.
In the case of the layout shown in FIG. 1, when the memory capacity or bit type of the memory macro section 3 is changed, the structure of the logic section 1 must also be changed accordingly. Thus, it takes a considerable period of time to design an LSI.
Further, in the memory-logic LSI shown in FIG. 1, the test control circuit for testing the memory macro section 3 is formed inside the logic section 1. When a test is carried out, an address signal and data are supplied to the memory macro section 3 from an external device outside the LSI chip 10 through the data input/output section 2 and the test control circuit of the logic section 1 (direct access system).
In the case of the layout shown in FIG. 1, if the structure of the logic section 1 is changed, it is necessary to redesign the test control circuit for testing the memory macro section 3, even if the structure of the memory macro section 3 is not changed.
As described above, whenever the logic section 1 is changed, the test control circuit for testing the memory macro section 3 must be changed. Therefore, it is difficult to form the conventional memory-logic LSI as an ASIC which meets a demand for a number of types in small quantities.